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Description:All voltages are referenced to ground. This is the absolute accuracy of the master oscillator frequency at the default settings with spread disabled. This is the change that is observed in master oscillator frequency with changes in voltage at TA = +25C. This is the change that is observed in master oscillator frequency with changes in temperature at VCC = 3.3V. The dither deviation of the master oscillator frequency is biderectional and results in an output frequency centered at the undithered frequency. This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally intro- duced to allow the oscillator to stabilize. tSTAB is equivalent to 512 master clock cycles and will depend on the pro- grammed master oscillator frequency. Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. CBtotal capacitance of one bus line in picofarads. EEPROM write time applies to all the EEPROM memory and SRAM shadowed EEPROM memory when WC = 0. The EEPROM write time begins after a stop condition occurs.